QEMU PRIP 45 - emulation of Microchip PIC32 microcontroller
- I'm working on port of 2.11bsd and 4.4bsd systems to pic32mx7 and pic32mz microcontrollers.
- For pic32mx7 and 2.11bsd (RetroBSD) I developed a free solution, based on VirtualMIPS project. It's still not architecturally full enough, and not quite accurate with respect to virtual memory features.
- For 4.4bsd port, currently I use a solution based on commercial OVPsim engine. Imperas offers a free 3-month license for personal use. OVPsim perfectly matches the hardware, and it helped a lot, but still keep seeking for a free solution.
My idea is to extend QEMU with all the features needed to simulate pic32mx7 and pic32mz families of microcontrollers.
Pic32mx7 has M4K processor with 128kbytes of static on-chip RAM and 512kbytes of program Flash memory.
Pic32mz has microAptivP processor with 512kbytes of static on-chip RAM and 2Mbytes of program Flash memory.
Both include an external interrupt controller (EIC), and a set of peripherals like UART ports, SPI, GPIO, optional Ethernet controller and others.
Various boards, based on these microcontrollers, have different port assignments, so it's better parameterize these features. From my experience, it makes sense to start with these boards:
- Microchip Explorer-16 board
- Microchip Multimedia Expansion Board II
- chipKIT Max32 board
- chipKIT WiFire board
- Geoff's Maximite Computer
- Need to add M4k and microAptivP cores to the table of supported MIPS cores.
- Need to implement an external interrupt controller mode (EIC). Pic32 microcontrollers work in EIC mode only. Currently EIC mode is not fully supported in QEMU.
- Pic32mx7 and pix32mz families have quite different memory maps, interrupt controllers and peripheral features. It makes sense to implement two separate platforms ("machines" in QEMU terminology), and several board variations for each platform.
- CPU clock frequency needs to be configurable per platform. Currently all MIPS cores are simulated with fixed frequency 200MHz. For pic32mx7 it must be 80MHz.
- Current implementation of TLBWR instruction is buggy. First of all, it does not take into account a value of Wired register. Second, it produces degenerated pseudo-random sequence in case of 16-entry TLB size. Should be fixed.
- Typical method to stop the processor is to use PAUSE instruction with all external interrupts disabled. It would be useful to terminate simulation in this case.