QEMU PRIP 3 - MIPS P5600 CPU emulation

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User stories[edit]

  • As a QEMU user I can run Linux kernel configured for MIPS P5600 CPU
  • As a QEMU user I'm able to obtain tools and build Linux kernel configured for MIPS 5600 CPU

Proposal[edit]

Set of MIPS32 R5 features which will allow QEMU to emulate MIPS P5600 CPU. For more details please refer to http://www.imgtec.com/mips/warrior/pclass.asp

Implementation details[edit]

40-bit XPA (Extended Physical Addressing)[edit]

Extended Physical Address (XPA) allows the physical address to be extended from 32-bits to 40-bits.

  • Extend CP0 registers EntryLo0, EntryLo1, LLAddr and TagLo from 32-bit to 64-bit on MIPS32
  • Add new instructions accessing upper 32-bits of extended registers: MFHC0 (move from high coprocessor 0) and MTHC0 (move to high coprocessor 0)
  • Enable PABITS=40

HTW (Hardware Table Walker)[edit]

Page Table Walking is the process by which a Page Table Entry (PTE) is located in memory. The mechanism can be used to replace the software handler for the TLB Refill condition. The existence of the Hardware Table Walking feature is denoted when Config3PW=1.

  • Add new HTW-specific registers: PWBase, PWField, PWSize, PWCtl
  • Implement hardware page table walking process

MAAR (Memory Accessibility Attribute Registers)[edit]

The MAAR register defines whether an instruction fetch or data load/store can speculatively access a memory region within the address bounds specified by MAAR. The MAARI register is used to specify a MAAR register number that may be accessed by software with an MTC0 or MFC0 instruction. Prior to access by MTC0 or MFC0, software must set MAARI.INDEX field to the appropriate value.

  • Add new registers MAAR and MAARI (probably this is sufficient as QEMU never does speculative access)

MSA (MIPS SIMD Architecture)[edit]

  • MSA has its own PRIP. It will be merged from separate feature branch.

VZ (Virtualization)[edit]

  • VZ will have its own PRIP. It will be merged from separate feature branch.

MIPS P5600[edit]

  • Add new CPU definition containing above features

Considerations[edit]

  1. Need to localize tools supporting MIPS32R5 and try to build and run Linux kernel configured for P5600 containing above features
  2. Virtualization is a big feature, it requires splitting into smaller features. This will be done in a separate PRIP dedicated for VZ.